The present invention relates to a phase locked loop (PLL), and, more particularly, to a system for reducing Voltage Controlled Oscillator (VCO) gain of a PLL.
A PLL is used to generate an oscillator signal based on an input reference signal. The oscillator signal has a phase that is directly related with the phase of the input reference signal. PLLs are widely used in modern electronic systems such as radios, telecommunication systems, computers, and so forth. In communication systems, the PLLs are used to generate oscillator signals that are used for modulation and demodulation of a message signal. In electronic circuits, PLLs generate oscillator signals that are used as clock signals for synchronous operation of the circuits. To generate an oscillator signal having a predefined phase characteristic, an input reference signal and a feedback signal derived from the oscillator signal are provided to the PLL. When a lock is achieved, the phase of the oscillator signal locks to the phase of the input reference signal in accordance with a predefined relationship. For example, the PLL may be programmed to generate an oscillator signal having a frequency that is an integral multiple of the frequency of the input reference signal.
Depending on the operating frequency range, the PLL may be programmed to generate an oscillator signal having a wide range of relationships with the input reference signal, as the operating frequency range has a direct relationship with the VCO gain (KVCO), where the higher the operating frequency range, the higher the VCO gain (KVCO). However, with an increase in the frequency range, the PLL becomes increasingly susceptible to variations in the input reference signal and VCO control voltage (supply or substrate injected). The reason for the increased susceptibility may be attributed to the high KVCO of the PLL. For example, in a PLL with high KVCO, such as KVCO=4000 MHz/V, a 1 mV variation in the input to the VCO control voltage (caused by variations in the input reference signal or supply/substrate noise) translates into a 4 MHz variation in the oscillator signal frequency. Such variations are not desirable when the oscillator signal is required to accurately follow a predefined relationship with the input reference signal. To overcome the above limitation, a PLL including both digital and analog calibration loops has been proposed.
Referring now to FIG. 1, a schematic diagram illustrating a PLL 100 with digital and analog calibration loops is shown. More particularly, the PLL 100 includes an analog calibration loop 102, a digital calibration loop 104, a phase-frequency detector (PFD) 106, a frequency divider 108, and a VCO 110. The analog calibration loop 102 includes a charge pump 112a and an analog filter 114, while the digital calibration loop 104 includes a charge pump 112b, a coarse analog-to-digital converter (ADC) 116, an optional integration stage 118, and a digital filter 120.
The frequency calibration of the PLL 100 is initiated by operating the PLL 100 in a digital calibration mode. To operate the PLL 100 in the digital calibration mode, the charge pump 112b is enabled and a reference voltage (Vref) is provided to the analog filter 114. This results in the analog filter 114 generating a constant bias voltage for the VCO 110 throughout the digital calibration mode. A switch ‘S’ is connected to a terminal T2 so that the output of the digital filter 120 is provided to the VCO 110. An oscillator signal is thus generated by the VCO 110 based on the inputs received from the analog filter 114 and the digital filter 120. The oscillator signal is then provided to the PFD 106 by way of the frequency divider 108 as a feedback signal. The frequency divider 108 reduces the frequency of the oscillator signal by a predetermined factor ‘N’ to generate the feedback signal. The PFD 106 also receives an input reference signal that is generated externally using a crystal oscillator. The PFD 106 compares the input reference signal and the feedback signal to generate either an UP signal or a DOWN signal. An UP signal is generated when the rising edge of the input reference signal leads the rising edge of the feedback signal. A DOWN signal is generated when the rising edge of the input reference signal lags the rising edge of the feedback signal. The UP signal represents an increase in the frequency of the oscillator signal and the DOWN signal represents a decrease in the frequency of the oscillator signal. The UP or the DOWN signal is transmitted to the charge pump 112b. The charge pump 112b drives a capacitor C1 that integrates the output of the charge pump 112b to convert the phase difference between the input reference signal and the feedback signal into a voltage.
The voltage at the terminal of the capacitor C1 is provided to the coarse ADC 116. The coarse ADC 116 generates digital signals corresponding to the voltage at the terminal of the capacitor C1. The digital signals may be passed through the optional integration stage 118. The optional integration stage 118 integrates the digital signals to increase the resolution. Thereafter, the output of the coarse ADC 116 (or the optional integration stage 118, if employed) is provided to the digital filter 120. The digital filter 120 averages the output signals from the coarse ADC 116 to generate digital control words for the VCO 110. The VCO 110 integrates the digital control word input to generate the oscillator signal.
The PLL 100 is operated in the digital calibration mode until the frequency of the oscillator signal (Fosc) is approximately equal to a required output frequency (Fout). For example, if Fout=500 MHz, the digital mode operation may be halted when Fosc=500.399 MHz. Thus, the digital calibration mode provides a coarse calibration of the PLL 100.
After the coarse calibration, the analog calibration mode is enabled. In this mode, the charge pump 112b is disabled and the switch ‘S’ is connected to the terminal T1, which results in the output of the coarse ADC 116 (or the optional integration stage 118, if employed) being provided to the VCO 110. Since the digital control word output of the digital filter 118 is unstable, it is preferred to provide the output of the coarse ADC 116 (or the optional integration stage 118, if used), which is a smoothed estimate of the output of the digital filter 120, as the digital control word for the VCO 110. The input from the coarse ADC 116 (or the optional integration stage 118) centers the frequency of the oscillator signal generated by the VCO 110 at Fosc. Additionally, Vref is disconnected from the analog filter 114 and the charge pump 112a is enabled. The charge pump 112a either supplies or extracts electric charge from the analog filter 114 depending on whether the UP or DOWN signal is output by the PFD 106. The analog filter 114 generates an output voltage, which when provided to the VCO 110, leads to fine adjustments in the frequency of the oscillator signal. As illustrated in the above example, the analog mode is initiated when the required output frequency is Fout=500 MHz and when the oscillator signal frequency has become Fosc=500.399 MHz. Thus, in the analog mode, the oscillator signal frequency requires small adjustments of the order of few KHz to achieve a phase lock. Since a small frequency range is required during analog calibration, the desired VCO gain, KVCO, to achieve this also is small, which reduces the susceptibility of the PLL to variations in the input reference signal and noise injected due to supply/substrate, thereby reducing jitter in the oscillator signal.
However, the above solution has several drawbacks. Since the digital loop 104 is realized using analog components, i.e., the charge pump 112b and the coarse ADC 116, the physical implementation of the circuit is complicated, leading to increased manufacturing costs and increased time-to-market. Further, the capacitor C1 used for sampling the output of the charge pump 112b increases the on-chip area of the circuit, which leads to an increase in product cost. Additionally, the PLL 100 includes a minimum of three poles, where the first pole is introduced by the capacitor C1, the second pole is introduced by the integrator after the coarse ADC 116, and the third pole is introduced by the VCO 110. Thus, to stabilize the PLL, the digital filter 120 must realize at least two zeros, which makes implementation of the digital filter 120 complicated. Therefore, it would be advantageous to have a PLL with reduced VCO gain as well as a simpler electronic circuit for enabling easier and less costly implementation.